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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66257FP M66257FP
5120 x 8-BIT 2 LINE MEMORY (FIFO) 5120 x 8-BIT x 2xLINE MEMORY (FIFO)
DESCRIPTION The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word x 8-bit double configuration which uses high-performance silicon gate CMOS process technology. It allows simultaneous output of 1-line delay data and 2-line delay data, and is most suitable for data correction over multiple lines. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between devices with different data processing throughput. FEATURES * Memory configuration of 5120 words x 8 bits x 2 (dynamic memory) * High-speed cycle ............................................. 25ns (Min.) * High-speed access ......................................... 18ns (Max.) * Output hold ........................................................ 3ns (Min.) * Fully independent, asynchronous write and read operations * Output .................................................................... 3 states * Q00 to Q07 ........................................................ 1-line delay * Q10 to Q17 ........................................................ 2-line delay APPLICATION Digital photocopiers, high-speed facsimile, laser beam printers.
PIN CONFIGURATION (TOP VIEW)
GND
1
36
VCC READ ENABLE INPUT READ RESET INPUT READ CLOCK INPUT WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT
Q00 2 Q01 3 Q02 4 Q03 5 Q04 6 Q05 7 Q06 8 DATA OUTPUT Q07 9 Q10 10 Q11 11 Q12 12 Q13 13 Q14 14 Q15 15 Q16 16 Q17 17 VCC 18
35 RE 34 RRES 33 RCK 32 WE 31 WRES 30 WCK
Outline 36P2R-A
M66257FP
29 28
GND VCC
27 D0 26 D1 25 D2 24 D3 23 D4 22 D5 21 D6 20 D7 19 GND DATA INPUT
BLOCK DIAGRAM
DATA INPUT D0 ~ D7 27 26 25 24 23 22 21 20
DATA OUTPUT Q00 ~ Q07
DATA OUTPUT Q10 ~ Q17
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
INPUT BUFFER
OUTPUT BUFFER
WRITE ADDRESS COUNTER
READ ADDRESS COUNTER
WRITE CONTROL CIRCUIT
READ CONTROL CIRCUIT
WRITE ENABLE INPUT
WE 32
35 RE
READ ENABLE INPUT
WRITE RESET INPUT WRES 31 WRITE CLOCK INPUT
MEMORY ARRAY OF 5120-WORD x 8-BIT x 2 CONFIGURATION 1-LINE DELAY DATA ONLY MEMORY/ 2-LINE DELAY DATA ONLY MEMORY
READ 34 RRES RESET INPUT READ CLOCK INPUT
WCK 30
33 RCK
VCC 18 VCC 28 VCC 36
1 GND 19 GND 29 GND
1
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
FUNCTION When write enable input WE is "L", the contents of data inputs D0 to D7 are written into 1-line delay data only memory in synchronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data only memory is also incremented simultaneously. The write functions given below are also performed in synchronization with rise edge of WCK. When WE is "H", a write operation to 1-line delay data only memory is inhibited and the write address counter of 1-line delay data only memory is stopped. When write reset input WRES is "L", the write address counter of 1-line delay data only memory is initialized. When read enable input RE is "L", the contents of 1-line delay data only memory are output to data outputs Q00 to Q07 and those of 2-line delay data only memory to data outputs Q10 to Q17 in synchronization with the rise of read clock input RCK. At this time, the read address counters of 1-line and 2-line delay data only memories is also incremented simultaneously.
Moreover, data of Q00 to Q07 are written into 2-line delay data only memory in synchronization with rise edge of RCK. At this time, the write address of 2-line delay data only memory is incremented. The read functions given below are also performed in synchronization with rise edge of RCK. When RE is "H", a read operation from both of 1-line delay data only memory and 2-line delay data only memory is inhibited and the read address counter of each memory is stopped. The outputs of Q00 to Q07 and Q10 to Q17 are in the high impedance state. Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay data only memory is stopped. When read reset input RRES is "L", the read address counter of 1-line delay data only memory, and the write address counter and read address counter of 2-line delay data only memory are initialized.
2
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70C, unless otherwise noted)
Symbol VCC VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Conditions A value based on GND pin Ta = 25C Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 660 -65 ~ 150 Unit V V V mW C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC GND Topr Parameter Supply voltage Supply voltage Operating ambient temperature Min. 4.5 0 Limits Typ. 5 0 Max. 5.5 70 Unit V V C
ELECTRICAL CHARACTERISTICS (Ta = 0 ~ 70C, VCC = 5V 10%, GND = 0V, unless otherwise noted)
Symbol VIH VIL VOH VOL IIH Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current Test conditions Min. 2.0 VCC-0.8 0.55 WE, WRES, WCK, RE, RRES, RCK, D0 ~ D7 WE, WRES, WCK, RE, RRES, RCK, D0 ~ D7 1.0 Limits Typ. Max. 0.8 IOH = -4mA IOL = 4mA VI = VCC Unit V V V V mA
IIL IOZH IOZL ICC CI CO
"L" input current Off state "H" output current Off state "L" output current Operating mean current dissipation Input capacitance Off state output capacitance
VI = GND
-1.0 5.0 -5.0 120 10 15
mA mA mA mA pF pF
VO = VCC VO = GND VI = VCC, GND, Output open tWCK, tRCK = 25ns f = 1MHz f = 1MHz
3
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO) SWITCHING CHARACTERISTICS (Ta = 0 ~ 70C, VCC = 5V 10%, GND = 0V, unless otherwise noted)
Symbol tAC tOH tOEN tODIS Access time Output hold time Output enable time Output disable time Parameter Min. 3 3 3 Limits Typ. Max. 18 18 18 Unit ns ns ns ns
TIMING CONDITIONS (Ta = 0 ~ 70C, VCC = 5V 10%, GND = 0V, unless otherwise noted)
Symbol tWCK tWCKH tWCKL tRCK tRCKH tRCKL tDS tDH tRESS tRESH tNRESS tNRESH tWES tWEH tNWES tNWEH tRES tREH tNRES tNREH tr, tf tH Parameter Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) "L" pulse width Input data setup time to WCK Input data hold time to WCK Reset setup time to WCK or RCK Reset hold time to WCK or RCK Reset nonselect setup time to WCK or RCK Reset nonselect hold time to WCK or RCK WE setup time to WCK WE hold time to WCK WE nonselect setup time to WCK WE nonselect hold time to WCK RE setup time to RCK RE hold time to RCK RE nonselect setup time to RCK RE nonselect hold time to RCK Input pulse rise/fall time Data hold time (Note 1) Min. 25 11 11 25 11 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
20 20
Note 1: For 1-line access, the following should be satisfied: WE "H" level period < 20ms - 5120 tWCK - WRES "L" level period RE "H" level period < 20ms - 5120 tRCK - RRES "L" level period 2: Reset the IC after power is turned on.
4
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
TEST CIRCUIT
VCC
RL=1k
Qn
SW1
CL=30pF : tAC, tOH
Qn SW2 CL=5pF : tOEN, tODIS RL=1k
Input pulse level : Input pulse rise/fall time : Decision voltage input : Decision voltage output :
0 ~ 3V 3ns 1.3V 1.3V (However, tODIS(LZ) is 10% of output amplitude and tODIS(HZ) is 90% of that for decision). The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
Parameter tODIS(LZ) tODIS(HZ) tOEN(ZL) tOEN(ZH)
SW1 Closed Open Closed Open
SW2 Open Closed Open Closed
tODIS/tOEN TEST CONDITION
3V RCK 1.3V 1.3V GND
3V RE GND tODIS(HZ) 90% 1.3V tOEN(ZH) VOH
Q0n Q1n
tODIS(LZ)
tOEN(ZL)
Q0n Q1n
1.3V 10% VOL
5
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
OPERATING TIMING * Write cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
WCK tWCK tWCKH tWCKL tWEH tNWES tNWEH tWES
WE
tDS tDH
tDS tDH
Dn
(n)
( n+1)
(n+2)
(n+3)
(n+4)
WRES = "H"
* Write reset cycle
Cycle n-1
Cycle n
Reset cycle
Cycle 0
Cycle 1
Cycle 2
WCK tWCK tNRESH tRESS tRESH tNRESS
WRES
tDS tDH
tDS tDH
Dn
(n-1)
(n)
(0)
(1)
(2)
WE = "L"
6
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
* Read cycle
Cycle n
Cycle n+1
Cycle n+2
Disable cycle
Cycle n+3
Cycle n+4
RCK tRCK tRCKH tRCKL tREH tNRES tNREH tRES
tAC RE
tODIS Q0n (n) Q1n (n+1) (n+2)
tOEN
HIGH-Z (n+3) tOH (n+4)
RRES = "H"
* Read reset cycle
Cycle n-1
Cycle n
Reset cycle
Cycle 0
Cycle 1
Cycle 2
RCK tRCK tNRESH tRESS tRESH tNRESS
RRES
tAC
Q0n (n-1) Q1n tON tON tON RE = "L" (n) (0) (0) (0) (1) (2)
7
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
* Note at WCK stop
n cycle
n+1 cycle
n cycle
Disable cycle
WCK tWCK tNWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n)
Period of writing data (n) into memory
Period of writing data (n) into memory
WRES = "H"
Input data Dn of n cycle is read at the rising edge after WCK of n cycle. Writing operation starts in the "L" period of WCK of n+1 cycle and ends at the rising edge after n+1 cycle. To stop reading write data at n cycle, input WCK for up to the rising edge of n+1 cycle. When the cycle next to n cycle is a disable cycle, input of WCK for a cycle is required after a disable cycle as well.
8
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
* Shortest read of data "n" written in cycle n Cycle n-1 on read side should be started after end of cycle n+1 on write side When the start of cycle n-1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid. In the figure shown below, the read of cycle n-1 is invalid.
Cycle n WCK
Cycle n+1
Cycle n+2
Cycle n+3
Dn
(n)
(n+1)
(n+2)
(n+3)
Cycle n-2
Cycle n-1
Cycle n
RCK
Qn
invalid
(n)
* Longest read of data "n" written in cycle n: 1-line delay Cycle n <1>* on read side should be started when cycle n <2>* on write is started Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each other.
Cycle n <1>* WCK
Cycle 0 <2>*
Cycle n <2>*
Dn
(n-1)<1>*
(n)<1>*
(0) <2>*
(n-1)<2>*
(n)<2>*
Cycle n <0>* RCK
Cycle 0 <1>*
Cycle n <1>*
Qn
(n-1)<0>*
(n)<0>*
(0)<1>*
(n-1)<1>*
(n)<1>*
<0>*, <1>* and <2>* indicates a line value.
9
MITSUBISHI DIGITAL ASSP
M66257FP
5120 x 8-BIT x 2 LINE MEMORY (FIFO)
APPLICATION EXAMPLE Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction.
M66257 D0 B Line (n+1) image data D7 Q00 Q07 x2
N Line n image data
1-line delay
Subtractor 2N-(A+B)
xK
Q10 Q17 2-line delay
A Line (n-1) image data
Secondary scanning direction
Primary scanning direction
A N B
Line (n-1) Line n Line (n+1) N' = N+K {(N-A)+(N-B)} = N+K { 2N-(A+B)} K : Laplacean coefficient
10
Adder A+B
Adder N+K {2N-(A+B)}
Corrected image data

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